Papers Accepted by HPCA 2025 and ISCA 2025!

Two papers on quantum computing architecture have been respectively accepted by conferences HPCA 2025 and ISCA 2025 🎉

Our paper BOSS: Blocking algorithm for optimizing shuttling scheduling in Ion Trap by Xian Wu, Chenghong Zhu, Jingbo Wang, and Xin Wang have been accepted by HPCA 2025, and paper S-SYNC: Shuttle and Swap Co-Optimization in Quantum Charge-Coupled Devices by Chenghong Zhu, Xian Wu, Jingbo Wang, and Xin Wang have been accepted by ISCA 2025.

For HPCA 2025: The International Symposium on High-Performance Computer Architecture (HPCA) is a premier forum for new ideas and research results in computer architecture. HPCA covers a wide range of topics, including processor architecture, storage systems, parallel computing, and emerging technologies.

For ISCA 2025: The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. ISCA covers a broad range of topics, including processor and memory architecture, parallelism, datacenter-scale computing, IoT, mobile and embedded architecture, power and energy, sustainable computing, and quantum computer architecture.

For the paper BOSS: Blocking algorithm for optimizing shuttling scheduling in Ion Trap: In this paper, we explore the critical role of shuttling operations within these systems, especially their influence on the fidelity loss and elongated execution times. To address these challenges, we have developed BOSS, an efficient blocking algorithm tailored to enhance shuttling efficiency. This optimization not only bolsters the shuttling process but also elevates the overall efficacy of ion trap devices. We experimented on multiple applications using two qubit gates up to 4000+ and qubits ranging from 64 to 78. Our method significantly reduces the number of shuttles on most applications, with a maximum reduction of 96.1%. Additionally, our investigation includes simulations of realistic experimental parameters that incorporate sympathetic cooling, offering a higher fidelity and a refined estimate of execution times that align more closely with practical scenarios.

For the paper S-SYNC: Shuttle and Swap Co-Optimization in Quantum Charge-Coupled Devices: In this paper, we introduce S-SYNC – a compiler designed to co-optimize the number of shuttling and swapping operations. S-SYNC exploits the unique properties of QCCD and incorporates generic SWAP operations to efficiently manage shuttle and SWAP counts simultaneously. Building on the static topology formulation of QCCD, we develop scheduling heuristics to enhance overall performance. Our evaluations demonstrate that our approach reduces the shuttling number by 3.69x on average and improves the success rate of quantum applications by 1.73x on average. Moreover, we apply S-SYNC to gain insights into executing applications across various QCCD topologies and to compare the trade-offs between different initial mapping methods.